Parallel ATA: diferència entre les revisions

|Namename = IDE: Integrated Drive Electronics <br/> PATA: Parallel Advanced Technology Attachment

|Typetype = massiu intern

|Imageimage = [[fitxer: Ata 20070127 002.jpg|150px]]

|Logologo = [[fitxer: ATA on mainboard.jpg|150px]]

|Captioncaption = Connector ATA femella en un cable a l'esquerra, dos connectors ATA en [[placa mare]] a la dreta

|Designerdesigner = [[Western Digital]]

|Design_datedesign_date = 1986

|Superseded_bysuperseded_by = [[Serial ATA]]

|Superseded_by_datesuperseded_by_date = 2003

|Externalexternal = no

|Hotplughotplug = no

|Data_signaldata_signal =

|Data_bit_widthdata_bit_width = 16 bits

|Data_bandwidthdata_bandwidth = 16 MB/s originalment <br/> Després 33, 66, 100, 133 i 166 MB/s

|Data_devicesdata_devices = 2 (mestre/esclau)

|Data_styledata_style = Paral·lel

|Data_data_|cable = Cable de cinta pla de 40 fils, posteriorment incrementat a 80 per seguretat.

|Num_pinsnum_pins = 40

|PIN1pIN1 = Reset

|Pin1_namepin1_name =

|PIN2pIN2 = Ground

|Pin2_namepin2_name =

|Pin3pin3 = Data 7

|Pin3_namepin3_name =

|Pin4pin4 = Data 8

|Pin4_namepin4_name =

|Pin5pin5 = Data 6

|Pin5_namepin5_name =

|Pin6pin6 = Data 9

|Pin6_namepin6_name =

|Pin7pin7 = Data 5

|Pin7_namepin7_name =

|Pin8pin8 = Data 10

|Pin8_namepin8_name =

|Pin9pin9 = Data 4

|Pin9_namepin9_name =

|Pin10pin10 = Data 11

|Pin10_namepin10_name =

|Pin11pin11 = Data 3

|Pin11_namepin11_name =

|Pin12pin12 = Data 12

|Pin12_namepin12_name =

|Pin13pin13 = Data 2

|Pin13_namepin13_name =

|Pin14pin14 = Data 13

|Pin14_namepin14_name =

|Pin15pin15 = Data 1

|Pin15_namepin15_name =

|Pin16pin16 = Data 14

|Pin16_namepin16_name =

|Pin17pin17 = Data 0

|Pin17_namepin17_name =

|Pin18pin18 = Data 15

|Pin18_namepin18_name =

|Pin19pin19 = Ground

|Pin19_namepin19_name =

|Pin20pin20 = Key o VCC_in

|Pin20_namepin20_name =

|Pin21pin21 = DDRQ

|Pin21_namepin21_name =

|Pin22pin22 = Ground

|Pin22_namepin22_name =

|Pin23pin23 = I/O write

|Pin23_namepin23_name =

|Pin24pin24 = Ground

|Pin24_namepin24_name =

|Pin25pin25 = I/O read

|Pin25_namepin25_name =

|Pin26pin26 = Ground

|Pin26_namepin26_name =

|Pin27pin27 = IOC HRDY

|Pin27_namepin27_name =

|Pin28pin28 = Cable select

|Pin28_namepin28_name =

|Pin29pin29 = DDACK

|Pin29_namepin29_name =

|Pin30pin30 = Ground

|Pin30_namepin30_name =

|Pin31pin31 = IRQ

|Pin31_namepin31_name =

|Pin32pin32 = No connect

|Pin32_namepin32_name =

|Pin33pin33 = addr 1

|Pin33_namepin33_name =

|Pin34pin34 = GPIO_DMA66_Detect

|Pin34_namepin34_name =

|Pin35pin35 = addr 0

|Pin35_namepin35_name =

|Pin36pin36 = addr 2

|Pin36_namepin36_name =

|Pin37pin37 = Xip select 1P

|Pin37_namepin37_name =

|Pin38pin38 = Xip select 3P

|Pin38_namepin38_name =

|Pin39pin39 = Activity

|Pin39_namepin39_name =

|Pin40pin40 = Ground